Click “Finish” to complete the new project wizard.For the Default Part window, select the “Boards” tab and then select the “ PicoZed 7030 SOM + FMC Carrier V2” and click “Next”.For the Project Type window, choose “RTL Project” and tick “Do not specify sources at this time”.I’ve created a folder named “kc705_aximm_pcie”. From the welcome screen, click “Create New Project”.Let’s kick off the design by creating a new project in Vivado and selecting the PicoZed 7Z030 as our target. From inside the ZIP file, copy the folder picozed_7030_fmc2 into the folder C:\Xilinx\Vivado\2015.4\data\boards\board_files of your Vivado installation.Download the PicoZed board definition files for Vivado 2015.4 from the PicoZed documentation page.The board definition files contain information about the hardware on the target board and also on how the Zynq PS should be configured in order to properly connect to that hardware. The first thing we have to do is provide the PicoZed board definition files to our Vivado installation so that the PicoZed will show up in the list of targets when we create a new project. the CDMA can access both the DDR3 memory and the PCIe address space.the PCIe end-point with bus mastering capability can access the DDR3 memory only (via M_AXI port of the AXI-PCIe bridge).the Zynq PS can access both the DDR3 memory and the PCIe address space.So again let’s look at who the bus masters are and what address spaces they can access: The reason is that a lot of the elements required in this design are hidden in the Zynq PS block, including the DDR3 memory controller, UART, Ethernet, Interrupt controller, Timer and QSPI. If you went through the previous tutorial where we created the same design for a Microblaze system, you may be wondering why the Zynq design seems so much simpler. It shows three main elements: the Zynq PS, the AXI to PCIe bridge and the AXI CDMA. The diagram below shows the block design we are about to build with only the AXI interfaces showing. Note: The tutorial text and screenshots are suitable for Vivado 2015.4 however the sources in the Git repository will be regularly updated to the latest version of Vivado. A JTAG programmer such as Digilent HS3 JTAG.An NVMe PCIe solid-state drive such as this one.To complete this tutorial you will need the following: We will then run PetaLinux on the FPGA and prepare our SSD for use under the operating system. In part 3, we will then test the design on the target hardware by running a stand-alone application which will validate the state of the PCIe link and perform enumeration of the PCIe end-points. In this second part of the tutorial series, we will build a Zynq based design targeting the PicoZed 7Z030 and PicoZed FMC Carrier Card V2. Part 3: Connecting an SSD to an FPGA running PetaLinux Part 2: Zynq PCI Express Root Complex design in Vivado (this tutorial) Part 1: Microblaze PCI Express Root Complex design in Vivado
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